1. Field of the Invention
The present invention relates in general to a high-frequency heating apparatus of a half-bridge type, and more particularly to an inverter power control circuit for the high-frequency heating apparatus which is capable of detecting conducting currents of free-wheeling diodes and setting ON times in accordance with the detected result, so that a zero voltage switching operation can stably be performed to control a power of an inverter.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a schematic view illustrating a conventional inverter control circuit for a high-frequency heating apparatus. As shown in this drawing, the conventional inverter control circuit comprises an inverter 1 for inducing a commercial alternating current (referred to hereinafter as AC) power to a high-frequency current in response to drive signals DS1 and DS2 to heat a container 2. To this end, the inverter 1 includes a bridge diode BD1, capacitors C1 and C2, a working coil HL1 and transistors Q1 and Q2.
The conventional inverter control circuit further comprises a phase comparator 3 for comparing phases of voltages at both sides A and B of the working coil HL1 in the inverter 1 with each other and outputting a signal in accordance with the compared result, an initializer 4 for generating a signal for initial driving of the inverter control circuit, a voltage detector 5 for detecting the voltages at both the sides A and B of the working coil HL1 in the inverter 1 and outputting a control signal in accordance with the detected result, a switching circuit 6 being switched in response to the control signal from the voltage detector 5 to select one of an output signal from the phase comparator 3 and an output signal from the initializer 4, a voltage controlled oscillator 7 for adjusting a phase of an oscillating frequency according to a level of an output signal from the switching circuit 6 and outputting the resultant signal, and an inverter driver 8 for outputting the drive signals DS1 and DS2 to the inverter 1 in response to an output signal from the voltage controlled oscillator 7 to drive it.
Referring to FIG. 2, there is shown a detailed circuit diagram of the initializer 4 and the voltage detector 5 in FIG. 1. As shown in this drawing, the initializer 4 includes a pulse generator 14 for generating a pulse, an analog switch 24 being switched in response to the pulse from the pulse generator 14, and a buffer 34 for buffering a voltage at a node between a capacitor C4 and a resistor R13 in response to the switching operation of the analog switch 24 and outputting the buffered voltage to the switching circuit 6.
The voltage detector 5 includes a first comparison circuit 15 for detecting the voltage at the one side A of the working coil HL1 in the inverter 1 and comparing the detected voltage with a zero voltage. To this end, the first comparison circuit 15 includes resistors R1 and R2 and a comparator CP1.
The voltage detector 5 further includes a second comparison circuit 25 for detecting the voltage at the other side B of the working coil HL1 in the inverter 1 and comparing the detected voltage with the zero voltage. To this end, the second comparison circuit 25 includes resistors R3 and R4 and a comparator CP2.
The voltage detector 5 further includes an exclusive-OR gate 35 for exclusive-ORing output signals from the first and second comparison circuits 15 and 25, and a signal delay circuit 45 for delaying an output signal from the exclusive-OR gate 35 for a predetermined time period. To this end, the signal delay circuit 45 includes a resistor R5 and a capacitor C3.
The voltage detector 5 further includes third and fourth comparison circuits 55 and 65. The third comparison circuit 55 includes resistors R6 and R7 for dividing a supply voltage Vcc, and a comparator CP3 for comparing an output signal from the signal delay circuit 45 with the divided voltage from the resistors R6 and R7. The fourth comparison circuit 65 includes resistors R8 and R9 for dividing the supply voltage Vcc, and a comparator CP4 for comparing the output signal from the signal delay circuit 45 with the divided voltage from the resistors R8 and R9.
The voltage detector 5 further includes an AND gate 75 for inputting output signals from the third and fourth comparison circuits 55 and 65 and the pulse from the pulse generator 14 in the initializer 4. The AND gate 75 also inputs the supply voltage Vcc through a resistor R12. Then, the AND gate 75 ANDs the inputted signals and outputs the resultant signal as the control signal to the switching circuit 6.
The operation of the conventional inverter control circuit for the high-frequency heating apparatus with the above-mentioned construction will hereinafter be described with reference to FIGS. 3A to 3G which are waveform diagrams of the input and output signals in the components in FIGS. 1 and 2.
First, for a time period T.sub.1 as shown in FIG. 3, in the initializer 4, the analog switch 24 is switched in response to an initial drive pulse from the pulse generator 14, thereby causing a voltage previously charged on the capacitor C4 to be applied to a non-inverting input terminal (+) of the buffer 34 which is an operational amplifier.
Because an output terminal of the buffer 34 is connected to an inverting input terminal (-) thereof, an output voltage therefrom is fed back to the inverting input terminal (-).
As a result, the voltage previously charged on the capacitor C4 is buffered by the buffer 34 according to the feedback operation of the buffer 34 and then applied to one fixed terminal b of a switch SW2 of the switching circuit 6.
At this time, in the switching circuit 6, a movable terminal c of the switch SW2 is connected to the one fixed terminal b thereof in response to the control signal which is generated from the voltage detector 5 as will be mentioned later in detail.
As the movable terminal c of the switch SW2 in the switching circuit 6 is connected to the one fixed terminal b thereof, the buffered voltage from the buffer 34 in the initializer 4 is transferred to the voltage controlled oscillator 7 through the switch SW2 in the switching circuit 6.
The voltage controlled oscillator 7 oscillates a frequency based on the voltage transferred through the switching circuit 6 and outputs the oscillating frequency to the inverter driver 8. In response to the output frequency from the voltage controlled oscillator 7, the inverter driver 8 outputs the drive signals DS1 and DS2 to the inverter 1. At this time, the drive signal DS1 from the inverter driver 8 is high in level as shown in FIG. 3G and the drive signal DS2 therefrom is low in level as shown in FIG. 3F.
In the inverter 1, the transistor Q1 is turned on in response to the high level drive signal DS1 from the inverter driver 8, whereas the transistor Q2 is turned off in response to the low level drive signal DS2 from the inverter driver 8.
On the other hand, the 110/220 V, 50/60 Hz commercial AC power is sequentially rectified and smoothed by the bridge diode BD1 and the capacitor C1. The resultant direct current (referred to hereinafter as DC) power is applied to the working coil HL1 through the turned-on transistor Q1.
As a result, the high-frequency current I.sub.K as shown in FIG. 3B flows through the working coil HL1, thereby causing a current to be induced in the container 2. The induced current generates a Joule heat in the container 2, so as to heat food contained in the container 2.
At this time, voltages with a phase difference of 90.degree. as shown in FIG. 3A appear at both the sides A and B of the working coil HL1.
Namely, a voltage as shown by a dotted line in FIG. 3A appears at the one side A of the working coil HL1 and a voltage as shown by a solid line in FIG. 3A appears at the other side B of the working coil HL1. At this time, the voltage appearing at the other side B of the working coil HL1 is a voltage being charged on the capacitor C2.
The voltage detector 5 detects the voltages at both the sides A and B of the working coil HL1 in the inverter 1 and outputs the control signal as a result of the detection to the switch SW2 in the switching circuit 6.
In detail, in the voltage detector 5, the voltage at the one side A of the working coil HL1 in the inverter 1 is supplied to the first comparison circuit 15. Then in the first comparison circuit 15, the supplied voltage is divided by the resistors R1 and R2 and then applied to a non-inverting input terminal (+) of the comparator CP1, an inverting input terminal (-) of which is applied with the zero voltage. The comparator CP1 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
The voltage at the other side B of the working coil HL1 in the inverter 1 is supplied to the second comparison circuit 25. Then in the second comparison circuit 25, the supplied voltage is divided by the resistors R3 and R4 and then applied to a non-inverting input terminal (+) of the comparator CP2, an inverting input terminal (-) of which is applied with the zero voltage. The comparator CP2 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
The exclusive-OR gate 35 exclusive-ORes the output values from the comparators CP1 and CP2 in the first and second comparison circuits 15 and 25 and outputs the resultant signal as shown in FIG. 3D. The output signal from the exclusive-OR gate 35 goes from low to high in level for the time period T.sub.1 as shown in FIG. 3D.
The output signal from the exclusive-OR gate 35 is delayed by a time constant of the resistor R5 and the capacitor C3 in the signal delay circuit 45 as shown in FIG. 3E and then applied in common to the third and fourth comparison circuits 55 and 65.
In the third comparison circuit 55, the supply voltage Vcc is divided by the resistors R6 and R7 and then applied to an inverting input terminal (-) of the comparator CP3, a non-inverting input terminal (+) of which is applied with the output voltage from the signal delay circuit 45. The comparator CP3 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
In the fourth comparison circuit 65, the supply voltage Vcc is divided by the resistors R8 and R9 and then applied to a non-inverting input terminal (+) of the comparator CP4, an inverting input terminal (-) of which is applied with the output voltage from the signal delay circuit 45. The comparator CP4 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
The output values from the comparators CP3 and CP4 are passed through resistors R10 and R11, respectively, and then added to the supply voltage Vcc passed through the resistor R12. The resultant value is applied to one input terminal of the AND gate 75.
The AND gate 75 also inputs the output value from the pulse generator 14 in the initializer 4 at its other input terminal. Then, the AND gate 75 ANDs the inputted values and outputs the resultant value as the control signal to the switch SW2 in the switching circuit 6. In response to the control signal from the AND gate 75, the movable terminal c of the switch SW2 in the switching circuit 6 is connected to the other fixed terminal a thereof.
On the other hand, the phase comparator 3 compares the phases of the voltages at both the sides A and B of the working coil HL1 in the inverter 1 with each other and outputs the signal as a result of the comparison to the other fixed terminal a of the switch SW2 in the switching circuit 6.
As the movable terminal c of the switch SW2 in the switching circuit 6 is connected to the other fixed terminal a thereof, the output signal from the phase comparator 3 is transferred to the voltage controlled oscillator 7 through the switch SW2 in the switching circuit 6. The voltage controlled oscillator 7 adjusts the phase of the oscillating frequency in response to the signal transferred through the switching circuit 6 and outputs the resultant oscillating frequency to the inverter driver 8.
In response to the oscillating frequency from the voltage controlled oscillator 7, the inverter driver 8 outputs the drive signals DS1 and DS2 to the inverter 1 for a time period T.sub.2 as shown in FIG. 3. At this time, the drive signal DS1 from the inverter driver 8 is low in level as shown in FIG. 3G and the drive signal DS2 therefrom is high in level as shown in FIG. 3F.
Then, in the inverter 1, the transistor Q1 is turned off in response to the low level drive signal DS1 from the inverter driver 8, whereas the transistor Q2 is turned on in response to the high level drive signal DS2 from the inverter driver 8.
As the transistor Q1 is turned off and the transistor Q2 is turned on, the voltage as shown by the dotted line in FIG. 3A appears at the one side A of the working coil HL1 and the voltage as shown by the solid line in FIG. 3A appears at the other side B of the working coil HL1. At this time, the voltage appearing at the other side B of the working coil HL1 is a voltage being discharged from the capacitor C2.
As a result, a current I.sub.P as shown in FIG. 3C flows through the transistor Q2.
On the other hand, the voltage detector 5 detects the voltages at both the sides A and B of the working coil HL1 in the inverter 1 and outputs the control signal as a result of the detection to the switch SW2 in the switching circuit 6.
Namely, in the voltage detector 5, the voltage at the one side A of the working coil HL1 in the inverter 1 is supplied to the first comparison circuit 15. Then in the first comparison circuit 15, the supplied voltage is divided by the resistors R1 and R2 and then applied to the non-inverting input terminal (+) of the comparator CP1, the inverting input terminal (-) of which is applied with the zero voltage. The comparator CP1 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
The voltage at the other side B of the working coil HL1 in the inverter 1 is supplied to the second comparison circuit 25. Then in the second comparison circuit 25, the supplied voltage is divided by the resistors R3 and R4 and then applied to the non-inverting input terminal (+) or the comparator CP2, the inverting input terminal (-) of which is applied with the zero voltage. The comparator CP2 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
Then, the exclusive-OR gate 35 exclusive-ORes the output values from the comparators CP1 and CP2 in the first and second comparison circuits 15 and 25 and outputs the resultant signal as shown in FIG. 3D. The output signal from the exclusive-OR gate 35 goes from high to low in level for the time period T.sub.2 as shown in FIG. 3D.
The output signal from the exclusive-OR gate 35 is delayed by the time constant of the resistor R5 and the capacitor C3 in the signal delay circuit 45 as shown in FIG. 3E and then applied in common to the third and fourth comparison circuits 55 and 65.
In the third comparison circuit 55, the supply voltage Vcc is divided by the resistors R6 and R7 and then applied to the inverting input terminal (-) of the comparator CP3, the non-inverting input terminal (+) of which is applied with the output voltage from the signal delay circuit 45. The comparator CP3 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
In the fourth comparison circuit 65, the supply voltage Vcc is divided by the resistors R8 and R9 and then applied to the non-inverting input terminal (+) of the comparator CP4, the inverting input terminal (-) of which is applied with the output voltage from the signal delay circuit 45. The comparator CP4 compares the inputted voltages at its inverting and non-inverting input terminals (-) and (+) with each other and outputs the resultant value.
The output values from the comparators CP3 and CP4 are passed through the resistors R10 and R11, respectively, and then added to the supply voltage Vcc passed through the resistor R12. The resultant value is applied to the one input terminal of the AND gate 75.
The AND gate 75 also inputs the output value from the pulse generator 14 in the initializer 4 at its other input terminal. Then, the AND gate 75 ANDs the inputted values and outputs the resultant value as the control signal to the switch SW2 in the switching circuit 6. In response to the control signal from the AND gate 75, the movable terminal c of the switch SW2 in the switching circuit 6 remains connected to the other fixed terminal a thereof.
On the other hand, the phase comparator 3 compares the phases of the voltages at both the sides A and B of the working coil HL1 in the inverter 1 with each other and outputs the signal as a result of the comparison to the other fixed terminal a of the switch SW2 in the switching circuit 6.
As the movable terminal c of the switch SW2 in the switching circuit 6 remains connected to the other fixed terminal a thereof, the output signal from the phase comparator 3 is transferred to the voltage controlled oscillator 7 through the switch SW2 in the switching circuit 6. The voltage controlled oscillator 7 adjusts the phase of the oscillating frequency in response to the signal transferred through the switching circuit 6 and outputs the resultant oscillating frequency to the inverter driver 8.
In response to the oscillating frequency from the voltage controlled oscillator 7, the inverter driver 8 outputs the drive signals DS1 and DS2 to the inverter 1 for a time period T.sub.3 as shown in FIG. 3. At this time, the drive signal DS1 from the inverter driver 8 is high in level as shown in FIG. 3G and the drive signal DS2 therefrom is low in level as shown in FIG. 3F.
Then, in the inverter 1, the transistor Q1 is turned on in response to the high level drive signal DS1 from the inverter driver 8, whereas the transistor Q2 is turned off in response to the low level drive signal DS2 from the inverter driver 8.
In this manner, the transistors Q1 and Q2 in the inverter 1 can accurately be turned on/off so that they can switch the zero voltage and a zero current.
In result, a switching frequency of the transistors Q1 and Q2 in the inverter 1 can automatically be in accord with the resonance frequency f.sub.o of the working coil HL1 and the capacitor C2 in the inverter 1 on the basis of the drive signals DS1 and DS2 from the inverter driver 8. Therefore, the power transfer can be performed at the maximum with no particular consideration of a capacity of the working coil HL1 which is greatly influenced by the induced current of the container 2.
Generally, the energy transfer can be carried out at the optimum under the condition of any container when the switching frequency of the inverter is in accord with the resonance frequency thereof.
As mentioned above, the switching operation can accurately be performed by the transistors Q1 and Q2 in the conventional inverter control circuit for the high-frequency heating apparatus. However, transistors in a conventional inverter power control circuit for the high-frequency heating apparatus are unable to perform accurately the above-mentioned switching operation.
Also in the conventional inverter power control circuit, the transistors may simultaneously be turned on due to an internal noise and a faulty operation of the circuit, resulting in a damage to the circuit. In order to prevent such a damage, a dead time or an interval that the transistors are simultaneously turned off is previously set in designing the circuit.
By the way, an energy path through the working coil and the resonance capacitor in the inverter may instantaneously be turned off in the dead time interval of the transistors, resulting in generation of a noise and a loss in the circuit. In order to solve such a problem, free-wheeling diodes FWD1 and FWD2 and capacitors C6 and C7 are connected in parallel to the switching devices Q1 and Q2 in the inverter, respectively, as shown in FIG. 4.
Current paths through the inverter in the dead time interval of the switching devices Q1 and Q2 in the inverter on the basis of the construction of FIG. 4 will hereinafter be described with reference to FIGS. 5A to 5D.
First, in the case where the switching device Q1 is turned on and the switching device Q2 is turned off, a current flows to the working coil HL1 and the resonance capacitor C2 through the turned-on switching device Q1.
Thereafter, when the switching device Q1 is turned off and the switching device Q2 remains at its OFF state, a current flows to a path for charging the capacitor C6, as shown in FIG. 5A.
From the moment that a voltage being charged on the capacitor C6 exceeds an input voltage Vdc, a reverse voltage is generated by the excess on the capacitor C7.
As the reverse voltage, for example, Vd is generated on the capacitor C7, a conducting voltage, namely, Vd is applied across the free-wheeling diode FWD2. As a result, a current flows through a repetitive loop of the free-wheeling diode FWD2, the working coil HL1 and the resonance capacitor C2 as shown in FIG. 5B.
At this time, the switching device Q2 is turned on under an external control when the free-wheeling diode FWD2 conducts. As a result, the current flows through the turned-on switching device Q2.
In the case where the switching device Q2 is turned off under the external control and the switching device Q1 remains at its OFF state, a current flows through a repetitive loop of the resonance capacitor C2, the working coil HL1 and the capacitor C7 as shown in FIG. 5C.
In this case, a voltage resulting from the current through the repetitive loop is charged on the capacitor C7. When the voltage being charged on the capacitor C7 exceeds the input voltage Vdc by the voltage Vd, a reverse voltage, namely, Vd is generated on the capacitor C6.
As a result, a conducting voltage, namely, Vd is applied across the free-wheeling diode FWD1, thereby causing a current to flow through a repetitive loop of the resonance capacitor C2, the working coil HL1 and the free-wheeling diode FWD1 as shown in FIG. 5D. At this time, the switching device Q1 is tuned on under the external control when the free-wheeling diode FWD1 conducts.
In this manner, the conventional inverter power control circuit for the high-frequency heating apparatus can perform the switching operation with no loss using the capacitors C6 and C7 and the free-wheeling diodes FWD1 and FWD2.
Also, in order to control the power of the inverter, the conventional inverter power control circuit is able to have a sufficient dead time interval to secure charging times of the capacitors C6 and C7, since the conducting currents of the free-wheeling diodes FWD1 and FWD2 flow until the voltages being charged on the capacitors C6 and C7 become equal to the input voltage Vdc, respectively.
However, the above-mentioned conventional inverter power control circuit has a disadvantage in that it must comprise a separate dead time setting circuit for providing the sufficient dead time interval to secure the charging times of the parallel capacitors to prevent the damage to the switching devices and meet the zero voltage switching condition of the switching devices.
Further in the conventional inverter power control circuit, the dead time interval necessary to the inverter may be different according to a variation in the input voltage and output voltages from the switching devices. For this reason, in the case where the dead time interval is set to a maximum value, conducting periods of the free-wheeling diodes may become too long after the charging of the parallel capacitors, resulting in an exaggerative increase in current stresses on the free-wheeling diodes.
For example, in the case where the switching devices have the same allowable peak current, the maximum output regulation is 95% when the dead time interval is 5%, and 90% when the dead time interval is 10%. As a result, an excessive dead time interval results in a limit in the regulation capability to the outputs of the switching devices and an increase in current stresses on the switching devices.